80A06 PatternSync Trigger Module

PatternSync Trigger Module for the DSA8200*1 Series
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Notice to EU customers

This product is not updated to comply with the RoHS 2 Directive 2011/65/ EU and will not be shipped to the EU. Customers may be able to purchase products from inventory that were placed on the EU market prior to July 22, 2017 until supplies are depleted. Tektronix is committed to helping you with your solution needs. Please contact your local sales representative for further assistance or to determine if alternative product(s) are available. Tektronix will continue service to the end of worldwide support life.

Features & Benefits

  • Enables 80SJNB – The Advanced Jitter, Noise, and BER Analysis Software
  • Provides Trigger on Repetitive Patterns from 2 to 223 Bits Long
  • Provides Buffered Clock Output for Input to a Phase Reference Module or other Devices
  • Accepts Clock from Clock Recovery Circuits (CR) in the 80A05 and 80A07 Electrical Clock Recovery Modules, and in the Optical Modules
  • Optional SlotSaver Adapter Provides Power and Control of the PatternSync Trigger Modules, External to the Mainframe, Saving Space for Additional Channels


  • When Used in Combination with 80SJNB: Characterizing Jitter, Noise, and BER Performance of High-speed Serial Designs from 1 Gb/s to 60 Gb/s Data Rates
  • Design Validation and Testing of Next-generation High-speed Serial Data Computer and Communications Components and Systems
  • When Used in Combination with 80SJNB: Jitter, Noise, and BER Analysis of Multi-gigabit Standards such as Fibre Channel, OIF CEI, XFP, UXPi, SATA, PCI, Physical Layer, XAUI, Gigabit Ethernet, Rapid I/O, InfiniBand, and Other Electrical or Optical Circuits
  • Enables Capture of Bits in a Repetitive Pattern for Bit Analysis When Only a Clock is Available for Triggering
  • Enables FrameScan™ of Repetitive Patterns When Only a Clock Signal is Available for Triggering

PatternSync Trigger Module

80A06 PatternSync Trigger module is required for the DSA8200 Series when using 80SJNB advanced Jitter, Noise, and BER Analysis software package. When this module is used with the 82A04 Phase Reference module, the jitter floor is ≤200 fsRMS.

The PatternSync Trigger Module is programmable to pattern lengths of up to 223 bits and accepts a user-supplied clock signal from 150 MHz to 12.75 GHz. The DSA8200 UI/PI for the 80A06 module offers pattern lengths from 2 to 223 bits and programs the module to within it's hardware range (a prescaler followed by a counter with minimum count of 30) for the least-common-multiple count.

Performance You Can Count On

Depend on Tektronix to provide you with performance you can count on. In addition to industry-leading service and support, this product comes backed by a one-year warranty as standard.

*1 Also compatible with TDS/CSA8200, TDS/CSA8000B, and TDS/CSA8000 sampling oscilloscopes. Not compatible with DSA8300. Order DSA8300 ADVTRIG Option for pattern synchronization in the DSA8300.




Acquisition Modes

Standard, Triggered Phase Reference, and FrameScan™

Compatible Mainframes

DSA8200, TDS/CSA8200, TDS/CSA8000B, and TDS/CSA8000 (Not compatible with DSA8300)

Mainframe Resources Required

One small (electrical) module slot, or TRIGGER PROBE POWER connector on the front panel of the oscilloscope (with available SlotSaver cable)

General Specifications



Input/Output Connectors

Precision 18 GHz SMA female connector

Input and Output Impedance

50 Ω

Absolute Maximum Input Voltage

2.0 Vp-p

Maximum DC Offset

±5.0 V DC

Input Electrical Return Loss

   50 MHz to 10 GHz

>15 dB

   10 GHz to 20 GHz

>10 dB

Input/Output Coupling

   Clock In


   Clock Out


   Trigger Out


Supported Clock Rates


150 MHz


12.5 GHz, 12.75 GHz (typical)

Prescaler Ratios

   Input clock (as selected in the UI/PI)

      150 MHz to 3.5 GHz


      3.5 GHz to 7 GHz


      7 GHz to 12.75 GHz


Programmable Pattern Length




223 (8,388,608)

Front-panel Output Amplitudes

   Clock Out (50 Ω AC coupled)

      150 MHz to 8.0 GHz

500 mVp-p (typical)

      8.0 GHz to 12.75 GHz

250 mVp-p (typical)

   Trigger Out (50 Ω DC coupled, ground referenced)

      Output High Level

0 V

      Output Low Level

–550 mV (typical)

Front-panel Output Rise and Fall Times

   Clock Out

<60 ps (faster for fast input slew rate)

   Trigger Out

<60 ps (faster for fast input slew rate)

System Jitter

   DSA8200, TDS/CSA8200, and TDS/CSA8000B with 80A06

<1.3 psRMS, 850 fs RMS (typical)

   TDS/CSA8000 with 80A06

<1.6 psRMS, 1.0 psRMS (typical)

   DSA8200 and TDS/CSA8200 with 80A06 and 82A04

≤200 fsRMS (determined by the 82A04, see 82A04 data sheet for more details)

Minimum Input Sensitivity

200 mVp-p

Physical Characteristics



















Environmental Conditions

Refer to the host instrument specification.


Refer to the host instrument specification.

Last Modified: 2011-08-22 05:00:00

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